Using Borland's command line tools

Using Borland's Command Line Tools
Page 6: Make Files 2

Installation, First Use	Multi-File Programs
Static Libraries	Static Linked and Dynamic Linked
Make Files [1], [2], [3], [4] [Summary]	Create and Use a DLL
Resource Files [1]

Here is a make file to build the example used for tlib, but without using a library [Tlib Example Code Link]

------makefile-----
123.exe : 123.obj one.obj two.obj three.obj
  bcc32 -WCR 123.obj one.obj two.obj three.obj

123.obj : 123.cpp numbers.h
  bcc32 -c -WCR 123

one.obj : one.cpp numbers.h
  bcc32 -c -WCR one

two.obj : two.cpp numbers.h
  bcc32 -c -WCR two

three.obj : three.cpp numbers.h
  bcc32 -c -WCR three
--------------------
The command to run the make file shown above is:
  make

The make file above will work but it is a lot of repetitive typing. There is an easier way.

If you put the directive .autodepend at the top of the make file starting at the left (with the period in column 1), then it will use the information the compiler placed into the object file to learn the header files upon which an object file depends. This removes the need to list numbers.h.

Each of the rules above is called an Explicit Rule because they explicitly list what the target is and what the dependencies are. There is another type of rule called an Implicit Rule. It specifies the extension of the target and the extension of the dependent file. The base file names of both are assumed to be the same. For example, here is an implicit rule and its associated command to build an object file from a same-base-name source file.

.cpp.obj :
  bcc32 -c -WCR $<

Make will replace the '$<' above with the name of the file upon which it depends. In this example that is the *.cpp file.

You can define simple macros for make to use. A macro will be replaced by the text it is assigned. The format of a macro definition is:

NAME=text that the macro will represent

When used after definition the macro name must be encased in '$()' as in $(NAME).

Using these things allows us to create the make file below to do the same job as the one above. It is much smaller than the original. Now that you know what the special items in it mean, it is just as easy to understand.

------makefile-----
.autodepend

OBJS=123.obj one.obj two.obj three.obj

123.exe : $(OBJS)
  bcc32 -WCR $(OBJS)

.cpp.obj :  # how to create a *.obj file from a *.cpp file
  bcc32 -c -WCR $<
--------------------

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